Verification by Error Modeling: Using Testing Techniques in Hardware Verification

Verification by Error Modeling: Using Testing Techniques in Hardware Verification Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design. Autor: Katarzyna Radecka, Zeljko Zilic Wydawnictwo: Springer-Verlag New York Inc. Rok wydania: 2010 Okładka: miękka Liczba stron: 216 Wymiary: 23.5 x 15.5 cm Ilustracje: XV, 216 p. Język: angielski ISBN: 9781441954022