Digital System Test and Testable Design: Using HDL Models and Architectures

Digital System Test and Testable Design: Using HDL Models and Architectures This book is about digital system testing and testable design. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Autor: Zainalabedin Navabi Wydawnictwo: Springer-Verlag New York Inc. Rok wydania: 2016 Okładka: miękka Liczba stron: 435 Wymiary: 25.4 x 17.8 cm Ilustracje: XVII, 435 p. Język: angielski ISBN: 9781489979278